Pyverilog
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function integer
The current parser may not be able to parse the code as below.
function integer funcname;
input invalue;
// ...
funcname = 0;
endfunction
Can confirm that I just ran into this issue as well. Additionally, the following will fail:
function funcname;
input integer invalue;
// ...
funcname = 0;
endfunction
It seems the parser only has a rule for width values in both of these positions, and not for real or integer type declarations here.
This still seems to be an open bug. What are the work arounds for this?
I'm now working on the SystemVerilog support of Pyverilog parser. This issue will be resolved in this update.