Support SVA assert/assume

[zhanghongce]

This pull request partially address the issue (https://github.com/PyHDI/Pyverilog/issues/87) as it adds support for assert property (...), always @(...) begin assert (...); end, assume property (...), always @(...) begin assume (...); end

Of course, some more work is needed in order to support @(posedge clk) inside the property.

[parker-research]

+1 - this would be a great feature to merge