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stdio.h error

Open GProtoZeroW opened this issue 8 years ago • 6 comments

Xilinx newbie, but I ran source build_all.tcl and ended up with

Xilinx/Vivado_HLS/2016.1/include/etc/ap_int_sim.h:75:10: fatal error: 'stdio.h' file not found
#include <stdio.h>
         ^
1 error generated.
Failed checking during preprocessing.
    while executing
"source [lindex $::argv 1] "
    ("uplevel" body line 1)
    invoked from within
"uplevel \#0 { source [lindex $::argv 1] } "

child process exited abnormally

Is this just a C HDL thing.

Also in a new overlay build instance once I add the IP I have wrapped my HDL(verilog, ect.) code in to block design can I just throw down a ZYNQ IP block without making any modifications to the ZYNQ IP. And this is assuming that in the vivado project setup I specified the PYNQ-Z1 board files and added the PYNQ-Z1 constraint file.

GProtoZeroW avatar Nov 11 '17 09:11 GProtoZeroW

This appears to be a problem with the Vivado environment which I've not seen before. Are you able to open Vivado HLS and create a design manually?

PeterOgden avatar Nov 14 '17 09:11 PeterOgden

Is HLS free, I use myHDL (python library) for my HDL (verilog) generation and then try to play the IP wrapper and block diagram games. Can you send me what TCL commands I need to have my Vivido project sent to you where I am doing the same workflow as the tutorial notebook Because I have had issues with generating the bitstream. Thanks ahead of time for working on some tutorials for the fabric. Any work on lowering the learning curve/barrier to FPGA design work for the PYNQ are going to make it a game changer

GProtoZeroW avatar Nov 15 '17 06:11 GProtoZeroW

HLS is included in the Webpack editions of Vivado so you should have access to it. What error are you getting when building the bitstream?

PeterOgden avatar Nov 23 '17 16:11 PeterOgden

Finaily Got some time to get back to this Started new HLS project , added the adder to project and specfied it as top cpp file I run the sythn and ~Xilinx/Vivado_HLS/2016.1/include/ap_int.h:74

#include <stdio.h>

GProtoZeroW avatar Dec 20 '17 20:12 GProtoZeroW

Could you just extract a Verilog file from HLs synth

GProtoZeroW avatar Dec 20 '17 20:12 GProtoZeroW

Nevermind got it working. I am going to say three things:

  1. if this helps me thank you
  2. Always check an export like this on another machine
  3. Over-abstraction is a bad thing. It's like math that doesn't show you have to calculate a number

GProtoZeroW avatar Dec 20 '17 20:12 GProtoZeroW