Integration of OpenHBMC in Vivado 2020.1 project

[DoychoBairov]

Hello, I am trying to integrate OpenHBMC into my Vivado 2020.1 design. Now the FIFO cores in OpenHBMC are downgraded for this Vivado version and everything is compiled for Artix-7 csg324 100t -1l. For clk_hbmc_0 and clk_hbmc_90 I set 200MHz and for clk_iserdes - 600MHz. The 600MHz setting in clk_wiz does not use an output buffer, OpenHBMC is set to use BUFIO+BUFR, 4ma, FAST, 46ohm. At this time my design has only MicroBlaze, periph_interconnect, mem_interconnect and uart.

With this settings the memory test failed.

In .xdc i have only PACKAGE_PIN and IOSTANDARD.

[AndreSch1982]

Hi!

With lower clock it is working?

[DoychoBairov]

In next compile i will try with lower clock.

[DoychoBairov]

Now i try with 100MHz for clk_hbmc_0/clk_hbmc_90 and 300MHz for clk_iserdes. Memory test is passed. TNS is 0.000 and WNS is 2.390. In previous compilation TNS and WNS was with different values in red.

[AndreSch1982]

I think issue is, that you are using speed grade 1 Artix,