夜云
May I ask whether this project supports the direct import of the netlist JSON file output by yosys at present? According to the previous conversation, I did not get a...
I will try this work and will contact you if there is any progress or difficulty. Finally, thank you for your contribution.
First of all, thank you for your team's contribution. I am indeed a user of yosys. My previous work was to render the netlist generated by yosys in vscode, which...
I think you can try `splice [options] [selection]` This command will adds `$slice` and `$concat` cells to the design to make the splicing of multi-bit signals explicit. This for example...
for example ```verilog module test(a, b, y); input [15:0] a, b; output [15:0] y; wire [7:0] ah = a[15:8], al = a[7:0]; wire [7:0] bh = b[15:8], bl = b[7:0];...
launch.tcl文件是临时文件运行时自动生成的，你是否配置了property.json文件？
新版本已经修复，请重新查看一下在你那是否有效
这个功能不是支持所有vhdl语法的，没反应就是说明你的vhdl有无法识别的语法，我忘记把报错提示输出了
最近在完善支持，遇到了一些麻烦，对于sv的支持后续会不断增加，毕竟我不是经常用sv，现在也在学，逐渐迭代。你也可以提一下你对sv的要求。
是的设计里面不能递归依赖，这样的话树结构会不断递归依赖自己导致内存溢出