Code refactoring

Open amitkulkarnis opened this issue 5 years ago • 4 comments

Is it possible to refactor a signal/port name present in multiple modules (files: *.v)?

Apr 27 '20 20:04 amitkulkarnis

I don't quite understand what you are saying, I hope you can give an example if possible. In addition, I think this is related to the code syntax, not to the plug-in.

Apr 28 '20 02:04 Nitcloud

E.g. if I want to change the name of a signal or port that is used in multiple HDL files then the refactor should take care of replacing the new name in corresponding places of all the modules.

Apr 28 '20 07:04 amitkulkarnis

I see what you mean. That's a good idea, but it's still hard for me to implement. I will consider adding this feature later.

Apr 28 '20 10:04 Nitcloud

@amitkulkarnis you can use the "change all current" to do that (provide by VSC)

Mar 06 '23 15:03 StrideZhou