[https://nvbugs/5567586][feat] Ampere xqa swa specdec for GPT-OSS Eagle3-one-model

[jhaotingc]

Summary by CodeRabbit

• New Features

  • Added sliding-window-aware attention masking, with per-tile masking and early exits when masking is unnecessary.

• Performance

  • Optimized mask computation and packing paths.
  • Improved warmup accuracy by using the device memory clock rate.
  • Updated memory prefetch to the newer CUDA API.

• Tests

  • Updated warmup utilities to accept device clock rate and reflect it in metrics.
  • Adjusted test harness and call sites to use the new warmup interface and prefetch flow.

Before this PR

GPT-OSS Eagle3-one-model TP=2

[11/25/2025-03:48:07] [TRT-LLM] [I] lm-eval gsm8k exact_match,flexible-extract accuracy: 62.09
[11/25/2025-03:48:07] [TRT-LLM] [I] Hypothesis testing report:
===========================================================
= ACCURACY HYPOTHESIS TESTING
===========================================================
Alpha (Type I:  False Positive): 0.050
Beta  (Type II: False Negative): 0.200
Sigma (Standard deviation): 50.000
#Samples: 1319
Higher is better: True
Theta (Minimum detectable effect): 4.841
Reference accuracy: 90.300
Threshold: 87.097
===========================================================
Evaluated accuracy: 62.092
===========================================================

After this PR

GPT-OSS Eagle3-one-model TP=2

[11/25/2025-02:55:53] [TRT-LLM] [I] lm-eval gsm8k exact_match,flexible-extract accuracy: 89.76
[11/25/2025-02:55:53] [TRT-LLM] [I] Hypothesis testing report:
===========================================================
= ACCURACY HYPOTHESIS TESTING
===========================================================
Alpha (Type I:  False Positive): 0.050
Beta  (Type II: False Negative): 0.200
Sigma (Standard deviation): 50.000
#Samples: 1319
Higher is better: True
Theta (Minimum detectable effect): 4.841
Reference accuracy: 90.300
Threshold: 87.097
===========================================================
Evaluated accuracy: 89.765
===========================================================

Description

Test Coverage

PR Checklist

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• PR Follows TRT-LLM CODING GUIDELINES to the best of your knowledge.

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• CODEOWNERS updated if ownership changes

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[coderabbitai[bot]]

📝 Walkthrough

Walkthrough

The patch updates cuda kernels and tests. It modifies applyMaskFromInput in cpp/kernels/xqa/mha.cu to add sliding-window-aware masking with conditional parameters and logic. Test utilities change warmup’s signature to accept clockRate, retrieve it via CUDA APIs, update prefetch calls, and propagate the new parameter across call sites.

Changes

Cohort / File(s)	Summary
XQA MHA sliding-window masking cpp/kernels/xqa/mha.cu	Extended applyMaskFromInput signature under SLIDING_WINDOW && !IS_SPEC_DEC_TREE to include tok0WinBeg, seqIter, cacheSeqLen, warpTileTokenBeg. Added per-CTA begMask computation, needMask short-circuit, clamped tokenRow, conditional packed mask assembly, and guarded interactions with SPEC_DEC. Updated call sites accordingly.
Test warmup API and CUDA attribute usage cpp/kernels/xqa/test/test.cpp, cpp/kernels/xqa/test/warmup.cu	Changed warmup signature to include int const& clockRate. test.cpp now queries cudaDevAttrMemoryClockRate, passes clockRate to warmup, and replaces prop.memoryClockRate usages. Adjusted cudaMemPrefetchAsync to use cudaMemLocation. warmup.cu computes nbCycles using clockRate.

Sequence Diagram(s)

sequenceDiagram
  autonumber
  participant K as kernel_mha_impl
  participant M as applyMaskFromInput
  participant ACC as Accumulator

  K->>M: applyMaskFromInput(warp, acc, mask, rowOffset, ..., headGrpSize[, tok0WinBeg, seqIter, cacheSeqLen, warpTileTokenBeg])
  rect rgb(240,248,255)
    note over M: Determine masking path
    M-->>M: Compute needMask (incl. sliding-window)
    alt needMask == false
      M-->>K: Return (no mask)
    else needMask == true
      M-->>M: Clamp tokenRow to actualQSeqLen
      opt SLIDING_WINDOW && !IS_SPEC_DEC_TREE
        M-->>M: Compute begMask per CTA
      end
      M-->>M: Load/assemble packed mask bits (conditional)
      M-->>ACC: Apply mask to accumulator tiles
      M-->>K: Return (masked)
    end
  end
  K-->>ACC: Continue with subsequent compute

sequenceDiagram
  autonumber
  participant T as test.cpp
  participant CUDA as CUDA Runtime
  participant W as warmup

  T->>CUDA: cudaDeviceGetAttribute(memoryClockRate)
  CUDA-->>T: clockRate
  T->>W: warmup(prop, clockRate, ms, stream?)
  W-->>W: nbCycles = f(clockRate, ms)
  T->>CUDA: cudaMemPrefetchAsync(..., cudaMemLocation{device/host}, flags=0)

Estimated code review effort

🎯 4 (Complex) | ⏱️ ~55 minutes

Pre-merge checks and finishing touches

❌ Failed checks (2 warnings)

Check name	Status	Explanation	Resolution
Docstring Coverage	⚠️ Warning	Docstring coverage is 0.00% which is insufficient. The required threshold is 80.00%.	You can run @coderabbitai generate docstrings to improve docstring coverage.
Description check	⚠️ Warning	PR description lacks required sections: missing formal PR title with ticket/type format, incomplete Description section (only shows 'Before/After' test results), missing explanation of implementation approach, and incomplete Test Coverage section.	Add PR title in format [TICKET][type] Summary, explain what changes were made and why in the Description section, detail the technical implementation (sliding window masking, warmup parameter changes), and clarify which tests validate the changes.

✅ Passed checks (1 passed)

Check name	Status	Explanation
Title Check	✅ Passed	The pull request title "[https://nvbugs/5567586][feat] Ampere xqa swa specdec for GPT-OSS Eagle3-one-model" accurately describes the main changes in the pull request. The title references sliding window attention (swa) and speculative decoding (specdec) support in XQA kernels, which directly corresponds to the code modifications shown in the changeset—specifically, the introduction of conditional sliding-window masking logic in mha.cu with speculative decoding guards, and supporting updates to test infrastructure. While the title includes metadata (bug tracker URL and feature label) which adds some noise, the core technical content clearly and specifically conveys the primary change and would be understandable to teammates familiar with the codebase.

✨ Finishing touches

• [ ] 📝 Generate docstrings

🧪 Generate unit tests (beta)

• [ ] Create PR with unit tests
• [ ] Post copyable unit tests in a comment

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[jhaotingc]

/bot run --disable-fail-fast

[tensorrt-cicd]

PR_Github #22697 [ run ] triggered by Bot. Commit: 4a34055

[tensorrt-cicd]

PR_Github #22697 [ run ] completed with state FAILURE. Commit: 4a34055

[jhaotingc]

/bot run --disable-fail-fast

[tensorrt-cicd]

PR_Github #22740 [ run ] triggered by Bot. Commit: c589e79

[tensorrt-cicd]

PR_Github #22740 [ run ] completed with state SUCCESS. Commit: c589e79 /LLM/main/L0_MergeRequest_PR pipeline #17146 completed with status: 'FAILURE'

[jhaotingc]

/bot run --disable-fail-fast

[tensorrt-cicd]

PR_Github #22806 [ run ] triggered by Bot. Commit: ff66d85

[tensorrt-cicd]

PR_Github #22806 [ run ] completed with state SUCCESS. Commit: ff66d85 /LLM/main/L0_MergeRequest_PR pipeline #17201 completed with status: 'FAILURE'

[jhaotingc]

Please make sure you locally tested special cases like multi-block mode.

Thanks @lowsfer, for Ampere XQA, the multi-block mode is not enabled yet in TRTLLM. But I did ran the XQA unit test. Some note is, there were some edge case that fails before I made my changes, those case are stayed failed (due to limited bandwidth 😅) But the overall accuracy ran by pipeline seemed good.

[jhaotingc]

/bot run

[tensorrt-cicd]

PR_Github #22916 [ run ] triggered by Bot. Commit: c738411

[tensorrt-cicd]

PR_Github #22916 [ run ] completed with state FAILURE. Commit: c738411 /LLM/main/L0_MergeRequest_PR pipeline #17284 completed with status: 'FAILURE'

[jhaotingc]

/bot run --disable-fail-fast

[tensorrt-cicd]

PR_Github #22921 [ run ] triggered by Bot. Commit: c738411

[tensorrt-cicd]

PR_Github #22921 [ run ] completed with state SUCCESS. Commit: c738411 /LLM/main/L0_MergeRequest_PR pipeline #17288 completed with status: 'FAILURE'

[farazkh80]

/bot run --disable-fail-fast

[tensorrt-cicd]

PR_Github #22935 [ run ] triggered by Bot. Commit: c738411

[pengbowang-nv]

Please make sure you locally tested special cases like multi-block mode.

Thanks @lowsfer, for Ampere XQA, the multi-block mode is not enabled yet in TRTLLM. But I did ran the XQA unit test. Some note is, there were some edge case that fails before I made my changes, those case are stayed failed (due to limited bandwidth 😅) But the overall accuracy ran by pipeline seemed good.

Can you share some examples of these failing tests? Thanks!

[tensorrt-cicd]

PR_Github #22935 [ run ] completed with state SUCCESS. Commit: c738411 /LLM/main/L0_MergeRequest_PR pipeline #17295 completed with status: 'FAILURE'

[farazkh80]

/bot run --disable-fail-fast

[tensorrt-cicd]

PR_Github #23070 [ run ] triggered by Bot. Commit: 2ebcb52

[farazkh80]

hey @pengbowang-nv, @jhaotingc recently went OOO until mid november. If the CI passes, could we merge this PR?

Can you share some examples of these failing tests? Thanks!

I tested the accuracy on RTX6000 MMLU as well and only a 2% drop with spec-dec compared to baseline. I think spec-dec slight accuracy degradation is an on-going discussion. @mikeiovine may have more context.

[tensorrt-cicd]

PR_Github #23070 [ run ] completed with state SUCCESS. Commit: 2ebcb52 /LLM/main/L0_MergeRequest_PR pipeline #17396 completed with status: 'FAILURE'

[farazkh80]

/bot run

[tensorrt-cicd]

PR_Github #23672 [ run ] triggered by Bot. Commit: 5a5467f

[tensorrt-cicd]

PR_Github #23672 [ run ] completed with state SUCCESS. Commit: 5a5467f /LLM/main/L0_MergeRequest_PR pipeline #17811 completed with status: 'FAILURE'

[farazkh80]

/bot run --test-backend "pytorch"

[tensorrt-cicd]

PR_Github #23766 [ run ] triggered by Bot. Commit: 5a5467f