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verified publisher icon Minres

Q: Un-aligned write

Open mslijepc opened this issue 2 years ago • 5 comments

Hi Eyck, not sure if there is a bug in this line:

https://github.com/Minres/SystemC-Components/blob/7d8a0173b219d684c80ba268086b31027d4a7402/src/bus_interfaces/axi/pin/axi4_initiator.h#L174C13-L174C13

In case we have e.g. 32B wide bus, we want to have single 4B write, with an offset 30, strb will be all zeros. How this write should be handled?

mslijepc avatar Jul 11 '23 16:07 mslijepc

I'll have a look...

eyck avatar Jul 12 '23 07:07 eyck

and also, data will be all zeros. Not sure, by the spec, if this should be done as burst?

mslijepc avatar Jul 12 '23 08:07 mslijepc

Hmm, I connot reproduce the issue although I tried hard ( found an issue with the second beat but not the first one) . This is what I get: grafik Did you attach an axi4_extension to the incoming transaction?

eyck avatar Aug 28 '23 06:08 eyck

Yes, axi4_extension was attached. How do you reproduce error, can you manually set address and len?

mslijepc avatar Sep 14 '23 05:09 mslijepc

Address and length are taken from the tlm_generic_payload so this way you can control it

eyck avatar Sep 14 '23 09:09 eyck