System-Bus-Design-Verilog
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Buddhimah
This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification
System-Bus-Design-Verilog
This is a Multi master Multi slave compatible system bus design modeled using verilog. This is much like AMBA AHB Specification
This is the full Architecture Diagram of the Bus
For More information please reffer AMBA Spec 2.0 Rev https://developer.arm.com/docs/ihi0011/latest/amba-specification-rev-20
Simulation results of this design are available on https://drive.google.com/file/d/1A_MhwQ1FTGPJf06GE6neZ6b-RiBfG8ux/view?usp=sharing
Buddhimah