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ARM-software
Arm C Language Extensions (ACLE)
I'm not sure if this is the case for all intrinsics with bottom and top and variants, but I think that it would be helpful to clarify in documentation that...
**Describe the bug** From https://arm-software.github.io/acle/neon_intrinsics/advsimd.html#vector-shift-left-and-widen, each neon vector shift left and widen intrinsic has a variant with `n == bit width`. For example: | Intrinsic|Argument preparation| |-|-| | int16x8_t [vshll_n_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s8)(int8x8_t...
**Describe the bug** In the "ADD, SUB, BFADD, BFSUB, FADD, FSUB (accumulate into ZA)" section, we guard half precision element operations [using __ARM_FEATURE_SME_F16F16 only](https://github.com/ARM-software/acle/blob/1622440cc8930729c2f014555b996e8c073553e9/main/acle.md?plain=1#L11274). However, "Two ZA single-vectors of half-precision...
**Thank you for submitting a proposal!** We are looking forward to evaluate your proposal, and if possible to make it part of the Arm C Language Extension (ACLE) specifications. We...
**Describe the bug** https://github.com/ARM-software/acle/blob/d294acf9fe429710151a166d12082a3434dfd764/cmse/cmse.md?plain=1#L1592 If `s` is zero, then `pe` is set just below `pb` -- or in case `pb` is zero, we wrap around 0 downwards, to the maximum...
It is encouraged to write loops using `svptest_first(svptrue(), pred = svwhilelt())`[1], instead of manually comparing `i < count` as the loop termination condition, as the predicate-generating `svwhilelt` already sets appropriate...
## Summary This proposal adds support for explicitly expressing the priority of function versions, in the target strings. ## Example use case For the case below, the default ordering has...
**Describe the bug** The [`vand_s64`](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s64) intrinsic says it compiles to `AND Dd,Dn,Dm`. https://github.com/ARM-software/acle/blob/c5d821bb32aa0b1f5e64df346b04ea0e3633ee18/tools/intrinsic_db/advsimd.csv#L1721 However, to my knowledge this instruction does not exist. There is no scalar variant documented: https://developer.arm.com/documentation/ddi0602/2025-03/SIMD-FP-Instructions/AND--vector---Bitwise-AND--vector-- It...
