CMSIS_6
CMSIS_6 copied to clipboard
ARM-software
CMSIS version 6 (successor of CMSIS_5)
- Added core_cxx.h files for ARMv8A, ARMV7R and ARMV8R based profiles - Moved gic peripheral to separate file - Moved __FPU_Enable function to the architecture specific file
In a previous issue submitted to CMSIS 5, I was told that it was no longer advisable to use the arch defines like `__ARM_ARCH_8M_MAIN__` and to instead use `__ARM_ARCH`. But...
Depends on CMSIS-Toolbox update
Hello! I think there is a need to add additional event in driver, "half buffer transfer" event. In NMEA applications it could be extremely helpful, to start parcing while dma...
When using gcc 11.3 & 12.3, there are sign conversion warnings in armv7m_cachel1.h with most usages of __SCB_DCACHE_LINE_SIZE and __SCB_ICACHE_LINE_SIZE in that file.
I get a warning/suggestion from the compiler because in the following function https://github.com/ARM-software/CMSIS_5/blob/a75f01746df18bb5b929dfb8dc6c9407fac3a0f3/CMSIS/Core/Include/core_cm7.h#L2195-L2199 in the line ```C uint32_t *vectors = (uint32_t *)SCB->VTOR; ``` the pointer `vectors` can/should be defines as...
In CMSIS/Core/Include/core_m33.h or CMSIS/Core/Include/core_starmc1.h, DWT related register define has been implemented, but BPU not.
CMSIS should contain an ANSI C compatible core header (e.g. `cmsis_none.h` or `cmsis_ansci.h`) which can be compiled on any major platform without anything vendor specific. In the spirit of the...
